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| AS4C1M16F5 (R) 5V 1Mx16 CMOS DRAM (fast-page mode) Features * Organization: 1,048,576 words x 16 bits * High speed - 50/60 ns RAS access time - 20/25 ns fast page cycle time - 13/17 ns CAS access time * Low power consumption - Active: 880 mW max (AS4C1M16E0-60) - Standby: 11 mW max, CMOS DQ * Fast page mode * 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh * Read-modify-write * TTL-compatible, three-state DQ * JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP II * 5V power supply * Industrial and commercial temperature available Pin arrangement SOJ Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Pin designation TSOP II VSS DQ16 DQ15 DQ14 DQ13 Pin(s) VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC Description Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Power Ground VSS DQ12 DQ11 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 A0 to A9 RAS DQ1 to DQ16 OE WE UCAS LCAS NC NC WE RAS A2 A3 Vcc A4 VSS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE VCC VSS A9 A8 A7 A6 A5 A4 VSS Selection guide Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum fast page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tAA tCAC tOEA tRC tPC ICC1 ICC5 AS4C1M16F5-50 50 25 13 13 84 20 170 2.0 AS4C1M16F5-60 60 30 17 15 104 25 160 2.0 Unit ns ns ns ns ns ns mA mA 4/11/01; v.0.9.1 Alliance Semiconductor P. 1 of 21 Copyright (c) Alliance Semiconductor. All rights reserved. AS4C1M16F5 (R) Functional description The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words x 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications. The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access. Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using: * RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence. * Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data. * CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). * Normal read or write cycles refresh the row being accessed. The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates with a single power supply of 5V 0.5V. The device provides TTL compatible inputs and outputs. Logic block diagram Refresh controller VCC GND RAS clock generator Column decoder Sense amp Data DQ buffers DQ1 to DQ16 RAS UCAS LCAS CAS clock generator WE WE clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Address buffers OE Row decoder 1024 x 1024 x 16 Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature Symbol AS4C1M16F5 AS4C1M16F5 Commercial Industrial VCC GND VIH VIL TA Min 4.5 0.0 2.4 -0.5 0 -40 Nominal 5.0 0.0 - - - - Max 5.5 0.0 VCC 0.8 70 85 Unit V V V V C VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. 4/11/01; v.0.9.1 Alliance Semiconductor P. 2 of 21 AS4C1M16F5 (R) Absolute maximum ratings Parameter Input voltage Input voltage (DQs) Power supply voltage Storage temperature (plastic) Soldering temperature x time Power dissipation Short circuit output current Symbol Vin VDQ VCC TSTG TSOLDER PD Iout Min -1.0 -1.0 -1.0 -55 - - - Max +7.0 VCC + 0.5 +7.0 +150 260 x 10 1 50 Unit V V V C o C x sec W mA DC electrical characteristics -50 Parameter Input leakage current Output leakage current Operating power supply current TTL standby power supply current Symbol IIL IOL ICC1 ICC2 Test conditions 0V Vin +5.5V, Pins not under test = 0V DOUT disabled, 0V Vout +5.5V RAS, UCAS, LCAS, Address cycling; -60 Min -5 -5 - - Max +5 +5 160 2.5 Unit A A mA mA 1,2 Notes Min -5 -5 - - Max +5 +5 170 2.5 tRC=min RAS = UCAS = LCAS VIH RAS cycling, UCAS = LCAS VIH, tRC = min of RAS low after XCAS low. RAS = VIL, UCAS or LCAS, address cycling: tPC = min RAS = UCAS = LCAS = VCC - 0.2V Average power supply current, RAS refresh mode ICC3 or CBR Fast page mode average power supply current CMOS standby power supply current Output voltage CAS before RAS refresh current - 170 - 160 mA 1 ICC4 ICC5 VOH VOL ICC6 - - 2.4 - - 120 2.0 - 0.4 170 - - 2.4 - - 110 2.0 - 0.4 160 mA mA V V mA 1, 2 IOUT = -5.0 mA IOUT = 4.2 mA RAS, UCAS or LCAS cycling, tRC = min 4/11/01; v.0.9.1 Alliance Semiconductor P. 3 of 21 AS4C1M16F5 (R) AC parameters common to all waveforms -50 Symbol tRC tRP tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tT tREF tCP tRAL tASC tCAH Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time RAS to CAS hold time CAS to RAS precharge time -60 Max - - 10K 10K 35 25 - - - - - 50 16 - - - Min 104 40 60 10 15 12 10 50 5 0 10 1 - 10 30 0 10 Max - - 10K 10K 43 30 - - - - - 50 16 - - - - Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 4,5 3 6 7 Min 84 30 50 8 15 12 10 40 5 0 8 1 - 8 25 0 8 Row address setup time Row address hold time Transition time (rise and fall) Refresh period CAS precharge time Column address to RAS lead time Column address setup time Column address hold time Read cycle -50 Symbol tRAC tCAC tAA tRCS tRCH tRRH -60 Max 50 13 25 - - - Min - - - 0 0 0 Max 60 17 30 - - - Unit Notes ns ns ns ns ns ns 9 9 6 6,13 7,13 Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Min - - - 0 0 0 4/11/01; v.0.9.1 Alliance Semiconductor P. 4 of 21 AS4C1M16F5 (R) Write cycle -50 Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Min 0 10 10 10 8 0 8 Max - - - - - - - Min 0 10 10 10 10 0 10 -60 Max - - - - - - - Unit ns ns ns ns ns ns ns 12 12 Notes 11 11 Read-modify-write cycle -50 Symbol tRWC tRWD tCWD tAWD Parameter Read-write cycle time RAS to WE delay time CAS to WE delay time -60 Max - - - - Min 135 77 35 47 Max - - - - Unit ns ns ns ns 11 11 11 Notes Min 113 67 32 42 Column address to WE delay time Refresh cycle -50 Symbol tCSR tCHR tRPC tCPT Parameter CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS) -60 Max - - - Min 5 10 0 10 Max - - - - Unit ns ns ns ns Notes 3 3 Min 5 8 0 10 RAS precharge to CAS hold time CAS precharge time (CBR counter test) 4/11/01; v.0.9.1 Alliance Semiconductor P. 5 of 21 AS4C1M16F5 (R) Fast page mode cycle -50 Symbol tCPA tRASP tPC tCP tPCM tCRW Parameter Access time from CAS precharge RAS pulse width -60 Max 28 100K - - - - Min - 60 35 10 85 60 Max 35 100K - - - - Unit ns ns ns ns ns ns Notes 13 Min - 50 30 10 80 54 Read-write cycle time CAS precharge time (fast page) Fast page mode RMW cycle Page mode CAS pulse width (RMW) Output enable -50 Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter CAS to output in Low Z RAS hold time referenced to OE OE access time OE to data delay -60 Max - - 13 - 13 - - 13 Min 0 10 - 15 0 10 0 0 Max - - 15 - 15 - - 15 Unit ns ns ns ns ns ns ns ns 8,10 8 Notes 8 Min 0 8 - 13 0 10 0 0 Output buffer turnoff delay from OE OE command hold time OE to output in Low Z Output buffer turn-off time 4/11/01; v.0.9.1 Alliance Semiconductor P. 6 of 21 AS4C1M16F5 (R) Notes 1 2 3 ICC1, ICC3, and ICC4 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) GND and VIH (max) VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS tWS (min) and tWH tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C1M16F5 5V devices. 4 5 6 7 8 9 10 11 12 13 14 15 16 AC test conditions - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns Dout 100 pF* +5V R1 = 828 R2 = 295 *including scope and jig capacitance GND Figure A: Equivalent output load Key to switching waveforms Rising input Falling input Undefined output/don't care 4/11/01; v.0.9.1 Alliance Semiconductor P. 7 of 21 AS4C1M16F5 (R) Read waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tASC tRCS tCAH tCAS UCAS, LCAS tRAD tASR tRAH Column address tRRH tRCH tRAL Address Row address WE tROH tROH tWEZ OE tRAC tAA tOEA tCAC tCLZ tREZ Data out tOLZ tOEZ tOFF (see note 11) DQ Upper byte read waveform tRC tRAS RAS tRCD tCSH tCRP UCAS tCRP LCAS tRAH tRAD tASR Address Row tRCS WE tROH OE tOLZ tAA tCAC tCLZ Upper DQ Lower DQ Data out tOFF tOEA tOEZ tREZ tWEZ tASC Column tRCH tRRH tRAL tCAH tRPC tCAS tRSH tCRP tRP tRAC 4/11/01; v.0.9.1 Alliance Semiconductor P. 8 of 21 AS4C1M16F5 (R) Lower byte read waveform tRAS tRC tRP RAS tRCD tCSH tCRP tCAS tRPC tASC tRAL tCAH Row tRCS Column tRCH tRRH tROH tWEZ tRSH tCRP LCAS tCRP UCAS tRAH tRAD tASR Address WE OE Upper DQ tRAC tAA tOLZ tOEA tOEZ tCAC tREZ tCLZ tOFF Data out Lower DQ Early write waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWP tWCS tWCH tCAS tRAL UCAS, LCAS Address Row address WE OE tDS tDH Data in DQ 4/11/01; v.0.9.1 Alliance Semiconductor P. 9 of 21 AS4C1M16F5 (R) Upper byte early write waveform tRC tRAS tRP RAS tASR tRAH tRAD tRAL Column address tASC tRCD tCSH tCRP tCAS tRPC tCWL tWCS tWCH tRWL tWP tCRP tCAH tRSH Row address Address UCAS tCRP LCAS WE OE tDS tDH Data in Upper DQ Lower DQ Lower byte early write waveform tRAS RAS tRAD tASR Address tRAH Column address tRPC tASC tRCD tCSH tCRP LCAS tRWL tCWL tWCS WE OE Upper DQ tDS Lower DQ Data in tDH tWCH tWP tRSH tCRP tCAH tCAS Row address tCRP UCAS tRAL tRC tRP 4/11/01; v.0.9.1 Alliance Semiconductor P. 10 of 21 AS4C1M16F5 (R) Write waveform tRC tRAS RAS tCSH tRSH tCRP UCAS, LCAS tRAD tRAH tASC tCAH Column address tRWL tCWL tWP WE tOEH OE tOED DQ tDS tDH tRAL tRCD tCAS tRP OE controlled tASR Address Row address Data in Upper byte write waveform tRC tRAS RAS tRAD tASR Address Row address tRAH Column address tCSH tRCD tCRP UCAS tCRP LCAS tCWL tRWL tWP WE tOEH OE tDS Upper DQ tOED Lower DQ Data in tDH tRPC tASC tRSH tCAH tCAS tCRP tRAL tRP OE controlled 4/11/01; v.0.9.1 Alliance Semiconductor P. 11 of 21 AS4C1M16F5 (R) Lower byte write waveform tRC tRAS tRP OE controlled RAS tRAD tASR tRAH tRAL Column address tRCD tCSH tCRP tACS tCRP tRSH tRPC tCWL tRWL tWP tCRP tCAH tCAS Address Row address LCAS UCAS WE tOEH OE Upper DQ tDS tDH Data in Lower DQ Read-modify-write waveform tRWC tRAS tRP tCAS tCRP tRCD tCSH tRSH RAS UCAS, LCAS tRAD tASR tRAH Row address tAR tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tWP tRWL Address WE OE tRAC tAA tCAC tCLZ tDS tDH Data in DQ tOLZ Data out 4/11/01; v.0.9.1 Alliance Semiconductor P. 12 of 21 AS4C1M16F5 (R) Upper byte read-modify-write waveform tRWC tRAS tRP RAS tCSH tRCD tCRP tCRP tCAS tRSH tCRP tRPC tACS tRAH UCAS LCAS tASR tRAD tRAL tCAH tCWL tRWL tCWD tOEA tWP Address Row Column address tRWD tAWD tRCS WE OE Upper input tCLZ tCAC tAA tRAC tOLZ tOED tDS Data in tOEZ tDH Upper output Data out tOED Lower input Lower output Lower byte read-modify-write waveform tRWC tRAS tRP tRPC tCSH tRCD tCRP tCAS tRSH tRAL tACS tRAH Row tCAH tCRP RAS tCRP UCAS LCAS tRAD tASR Address Column address tRWD tAWD tRCS tCWD tOEA tCWL tRWL tWP WE OE Upper input Upper output Lower input tRAC tAA tCAC tCLZ tOLZ tOED tDH tOED tDS Data in tOEZ Data out Lower output 4/11/01; v.0.9.1 Alliance Semiconductor P. 13 of 21 AS4C1M16F5 (R) Fast page mode read waveform tRASP RAS tCSH tCRP CAS tAR tRAD tASR Address tRAH Row Column tRCS WE tOEA OE tRAC tCLZ tAA I/O Data out tOEZ tCAP tOFF Data out tCAC Data out tOEA tRCH tASC Column tRCS tRAL tCAH Column tRCH tRRH tRCD tCAS tCP tPC tRSH tRP Fast page mode byte write waveform tRASP RAS tPCM tCSH tRCD CAS tASR Address Row tRCS WE tOEA OE tAA tRAC tCLZ tCAC I/O Data out Data in tDS tCLZ tCAC Data in Data out tDH tDS tCAP tCLZ tCAC Data in Data out tOEZ tOED tOEA tRAD tRAH tCAH Column tRWD tCWD tAWD Column tCWL tCWD tCWD tAWD tWP tCAH tRAL tCAH Column tRWL tCWL tCAS tCP tCRP tRP 4/11/01; v.0.9.1 Alliance Semiconductor P. 14 of 21 AS4C1M16F5 (R) Fast page mode early write waveform tRASP tRAH RAS tCRP tRCD tCSH tCAS CAS tAR tASR Address Row tRAD Column Column Column tCWL tWP tWCH WE OE tHDR tDS I/O Data In tDH Data in Data in tOED tOEH tRAL tASC tWCS tCP tRSH tPC tCAH tRWL CAS before RAS refresh waveform tRC tRP RAS tRPC tCP tCSR UCAS, LCAS DQ OPEN tCHR tRAS WE = VIH RAS only refresh waveform tRC tRAS RAS tCRP UCAS, LCAS Address tASR Row address tRAH tRPC tRP WE = OE = VIH or VIL 4/11/01; v.0.9.1 Alliance Semiconductor P. 15 of 21 AS4C1M16F5 (R) Hidden refresh waveform (read) tRC tRAS RAS tCRP tRCD CAS tRAD tRAH tASR Address Row tRCS WE tOEA OE tRAC tAA tCAC tCLZ DQ Data out tOEZ tOFF tASC Col address tRRH tAR tCAH tRSH tCHR tCRP tRP tRAS tRC tRP Hidden refresh waveform (write) tRC tRAS RAS tCRP UCAS, LCAS tRAD tRAH tASR Address Row address tWCR tWP tWCS WE tDS tDHR DQ OE Data in tDH tWCH tASC Col address tRWL tRAL tCAH tAR tRCD tRSH tCHR tRP 4/11/01; v.0.9.1 Alliance Semiconductor P. 16 of 21 AS4C1M16F5 (R) CAS before RAS refresh counter test waveform tRAS tRSH RAS tCSR UCAS, LCAS tASC tCAH Address Col address tAA tCAC tCLZ DQ Read cycle tRCS WE tROH tOEA OE tRWL tCWL tWP tWCH tWCS Write cycle WE tDH tDS DQ OE tRCS tCWD tAWD WE Read-Write cycle tOEA OE t AA tCLZ tCAC DQ Data out tOEZ tDS Data in tDH tRWL tWP tCWL Data in Data out tRRH tRCH tOFF tOEZ tRAL tCHR tCPT tCAS tRP tOED 4/11/01; v.0.9.1 Alliance Semiconductor P. 17 of 21 AS4C1M16F5 (R) Package dimensions 42-pin SOJ 400 mil Min Max c SOJ E1 E2 e D Pin 1 E B A A1 b A2 Seating Plane A A1 A2 B b c D E E1 E2 e 0.128 0.148 0.025 0.105 0.115 0.026 0.032 0.015 0.020 0.007 0.013 1.070 1.080 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 c 50-pin TSOP II Min Max (mm) (mm) 1.2 0.05 0.95 1.05 0.30 0.45 0.12 0.21 20.85 21.05 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60 TSOP II E He 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 d l A A1 A2 b c d E He e l A A1 b e A2 0-5 4/11/01; v.0.9.1 Alliance Semiconductor P. 18 of 21 AS4C1M16F5 (R) Typical DC and AC characteristics 1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0 Ta = 25C Normalized access time Normalized access time tRAC vs. supply voltage VCC 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Typical access time Normalized access time tRAC vs. ambient temperature Ta 100 90 80 -70 70 60 50 40 30 50 100 150 200 Load capacitance (pF) 250 -60 -50 Typical access time tRAC vs. load capacitance CL 170 160 Supply current (mA) 150 140 130 120 110 100 4.0 Typical supply current ICC vs. supply voltage VCC 170 160 Supply current (mA) 150 140 130 120 110 Typical supply current ICC vs. ambient temperature Ta 35 30 Power-on current (mA) Typical power-on current IPO vs. cycle rate 1/tRC -50 -60 25 20 15 10 5 0.0 2 4 6 8 Cycle rate (MHz) 10 -50 -60 4.5 5.0 5.5 Supply voltage (V) Typical refresh current ICC3 vs. supply voltage VCC 6.0 100 -55 -10 35 80 125 Ambient temperature (C) Typical refresh current ICC3 vs. Ambient temperature Ta 160 140 Refresh current (mA) 120 100 80 60 40 20 4.0 160 140 Stand-by current (mA) Refresh current (mA) -50 -60 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 20 40 60 80 Ambient temperature (C) Typical TTL stand-by current ICC2 vs. supply voltage VCC -50 -60 120 100 80 60 40 4.5 5.0 5.5 Supply voltage (V) 6.0 20 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0 4/11/01; v.0.9.1 Alliance Semiconductor P. 19 of 21 AS4C1M16F5 (R) 3.5 3.0 Stand-by current (mA) 2.5 2.0 1.5 1.0 0.5 0.0 Typical TTL stand-by current ICC2 vs. ambient temperature Ta Output sink current (mA) 70 60 50 40 30 20 10 0.0 0.0 Typical output sink current IOL vs. output voltage VOL Output source current (mA) 0.5 1.0 1.5 Output voltage (V) 70 60 50 40 30 20 10 0.0 2.0 Typical output source current IOH vs. output voltage VOH 0 20 40 60 80 Ambient temperature (C) 0.0 1.0 2.0 3.0 Output voltage (V) 4.0 Hyper page mode current (mA) 120 100 80 60 40 20 0.0 0 20 40 60 80 Ambient temperature (C) -50 -60 Hyper page mode current (mA) Typical hyper page mode current ICC4 vs. ambient temperature Ta 140 Typical hyper page mode current ICC4 vs. supply voltage VCC 140 120 100 80 60 40 20 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0 -50 -60 Capacitance 15 Parameter Input capacitance DQ capacitance Symbol CIN1 CIN2 CDQ Signals A0 to A9 RAS, UCAS, LCAS, WE, OE = 1 MHz, Ta = Room temperature Test conditions Max Unit Vin = 0V Vin = 0V Vin = Vout = 0V 5 7 7 pF pF pF DQ0 to DQ15 AS4C1M16F5 ordering information Package \ RAS access time Plastic SOJ, 400 mil, 42-pin TSOP II, 400 mil, 44/50-pin 5V 5V 50 ns AS4C1M16F5-50JC AS4C1M16F5-50JI AS4C1M16F5-50TC AS4C1M16F5-50TI 60 ns AS4C1M16F5-60JC AS4C1M16F5-60JI AS4C1M16F5-60TC AS4C1M16F5-60TI 4/11/01; v.0.9.1 Alliance Semiconductor P. 20 of 21 AS4C1M16F5 (R) AS4C1M16F5 part numbering system AS4 DRAM prefix C C = 5V CMOS 1M16E0 -XX X X Device number RAS access time Package: Temperature range C=Commercial, 0C to 70C J = 42-pin SOJ 400 mil T=44/50-pin TSOP II 400 mil I=Industrial, -40C to 85C 4/11/01; v.0.9.1 Alliance Semiconductor P. 21 of 21 |
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